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PCB DESIGN SERVICESSI & PI Analysis
SI & PI Analysis
Services.
Predictive simulation and optimization for high-speed digital and high-frequency communication protocols.
At Qmax Systems, Signal Integrity and Power Integrity analysis are embedded into every phase of the PCB design workflow — from initial interface selection and stackup definition, through constraint-driven layout, to post-layout verification and fabrication release. Our first-time-right methodology means that failure mechanisms are identified and engineered out before a board is sent to fabrication, not discovered during prototype bring-up.
Our SI/PI engineering team has more than three decades of hands-on experience with the full spectrum of ultra-high-speed digital signaling: NRZ interfaces from 10Gbps to 56Gbps, PAM4 channels at 56Gbps through 224Gbps per lane, multi-lane switch fabrics, complex DDR memory subsystems, and high-current power delivery networks for AI compute, data centre networking, and server platforms.
SI/PI analysis is available both as a standalone engineering service and as an integrated component of our PCB Design and Hardware Development programs. All design IP, simulation data, and deliverables remain the sole intellectual property of the customer.
1. Introduction to SI/PI Analysis
Modern PCB design operating above 1Gbps per lane is an applied electromagnetic engineering discipline. As signal edge rates shrink below 50 picoseconds and PAM4 modulated lanes carry 112Gbps or 224Gbps of data, the physical PCB becomes a transmission-line network where every via transition, anti-pad geometry, reference plane discontinuity, laminate dielectric property, and decoupling capacitor placement directly determines system functional margin. A board that passes visual inspection and DRC can still fail first-pass bring-up because of an under-specified stackup, an unmodelled via stub resonance, or an inadequate PDN that collapses under peak transient load.
SI and PI are tightly coupled disciplines that Qmax treats as a single engineering system, not two separate checks. PDN switching noise injected into reference planes raises the noise floor at high-speed receivers, directly degrading eye diagram margin. Ground bounce from simultaneous switching outputs (SSO) across a high-density ASIC I/O bank adds jitter to differential SerDes lanes sharing the same power domain. A well-designed PDN with sub-milliohm AC impedance from DC through the GHz regime is as critical to achieving a clean PAM4 eye diagram as controlling the channel insertion loss (SDD21) and near-end crosstalk (NEXT).
1.1 Signal Integrity — Engineering Scope
Signal Integrity analysis ensures that digital signals arrive at their destination with sufficient voltage margin, timing margin, and noise immunity to meet the BER (Bit Error Rate) specification of the interface. At Qmax Systems, SI analysis covers the full chain from silicon pad to silicon pad:
- Transmission-line impedance control and controlled-impedance stackup: Every high-speed net is modelled as a distributed transmission line. Characteristic impedance (Z0) for single-ended and differential pairs is calculated using 2D/2.5D field solvers with real dielectric constant (Dk) and dissipation factor (Df) values at the operating frequency — not generic 1MHz datasheet figures. For PAM4 channels on Megtron 6 or Tachyon 100G, this distinction in Dk/Df at 10–16GHz directly determines whether the channel insertion loss (SDD21) meets the compliance mask.
- Via stub resonance analysis and back-drill specification: Unterminated via stubs below the last active signal connection act as quarter-wave resonators. Stub resonant frequency is governed by stub length and local dielectric constant. At PCIe Gen6 (64GT/s PAM4) or 112G PAM4 Ethernet, stubs longer than 8–12 mils on standard server board thicknesses create insertion loss notches within the signalling bandwidth, failing COM (Channel Operating Margin) requirements. Qmax performs via stub analysis for every design above 16GT/s and specifies controlled-depth back-drilling accordingly.
- End-to-end IBIS-AMI channel simulation: For NRZ interfaces at PCIe Gen5 speeds and all PAM4 interfaces, eye diagram simulation requires IBIS-AMI models that capture transmitter FFE (Feed-Forward Equalization), receiver CTLE (Continuous Time Linear Equalization), and DFE (Decision Feedback Equalization) behaviour accurately. We obtain these models directly from silicon vendors and run statistical eye simulations (QuickEye / StatEye) to extract eye height, eye width, and BER bathtub curves referenced against the specification compliance mask.
- COM (Channel Operating Margin) analysis: For PCIe Gen5/6 and 112G/224G PAM4 Ethernet, channel compliance is assessed using IEEE COM methodology, which accounts for channel IL, integrated crosstalk noise (ICN from NEXT and FEXT), equalization, jitter, and noise in a single figure of merit. COM ≥ 3dB is the pass threshold. ICN — the statistical aggregate of all aggressor lane crosstalk contributions — is a primary constraint that drives inter-pair spacing, reference plane continuity, and via placement discipline.
- Crosstalk extraction and mixed-mode S-parameter analysis: Full mixed-mode S-parameter sets (SDD21, SDD11, SCD21, SDDS41) are extracted from 3D EM models for all critical differential channels. Mode conversion (SCD21) — differential-to-common-mode energy conversion caused by asymmetric routing or P/N via geometry — is a key EMI mechanism and a jitter contributor that is explicitly tracked and minimised.
- TDR simulation for impedance discontinuity identification: Time-domain reflectometry simulation generates an impedance-versus-time profile of a signal path, revealing BGA fanout via mismatches, anti-pad geometry effects, connector footprint discontinuities, and reference plane transitions. TDR simulation is used iteratively to refine via design rules before they are locked into the PCB constraint file.
1.2 Power Integrity — Engineering Scope
Power Integrity analysis ensures the PDN (Power Distribution Network) delivers stable, low-impedance supply voltage to every device across the full operating frequency range — from DC through the GHz regime. An inadequately designed PDN causes supply voltage droop under transient load, generates switching noise that couples into SI channels through shared reference planes, and produces harmonic emissions that cause EMI compliance failures.
- DC IR drop analysis: Static DC current distribution is simulated across copper pours, plane splits, via arrays, and connector contacts to map voltage drop across the board. For multi-phase CPU VCC rails exceeding 200A, GPU power domains at 300–700W, or high-current bus converters in power electronics systems, IR drop analysis identifies hotspots, optimises copper pour geometry and weight, and ensures node voltages remain within the silicon vendor's specified tolerance across all load conditions.
- PDN AC impedance profiling and anti-resonance suppression: The PDN presents a frequency-dependent impedance to each load. Resonant peaks between bulk electrolytic capacitors, ceramic decoupling capacitors, and PCB plane inductance create supply voltage spikes when the load switches. We simulate PDN impedance from DC to 1GHz+, targeting a flat profile below Ztarget = ΔV/ΔI across the full frequency range. Anti-resonance peaks are suppressed through calculated intermediate-value capacitor interleaving, ESL-optimised placement, and — where required — resistive damping networks.
- Decoupling capacitor optimisation: Capacitor placement is a quantitative calculation, not a rule of thumb. We calculate the effective mounted inductance (ESL) of each capacitor location based on via count, land geometry, and distance to the device power pads, then select C0G/NP0 or X7R capacitor values to achieve broadband PDN coverage. For CPU and GPU packages, on-die capacitance (Cdie) and package inductance (Lpkg) are incorporated into the PDN model using silicon-vendor-supplied package parasitic data.
- Power plane resonance and EBG analysis: Power-ground plane pairs form a parallel-plate resonant cavity. Cavity resonances at frequencies determined by board dimensions and Dk create PDN impedance peaks that peripheral decoupling capacitors cannot suppress. Where resonances fall within the PDN bandwidth of concern, we apply EBG (Electromagnetic Band Gap) structures, resistive plane edge termination, or plane segmentation.
- High-current trace and via current capacity: Trace current density is analysed against IPC-2152 for all power-carrying conductors, accounting for copper weight, ambient temperature, and thermal management. Via arrays in high-current paths are calculated for aggregate current capacity including temperature derating. This is particularly critical for power electronics boards, heavy copper designs (4oz+), and AI accelerator power delivery networks.
1.3 Why Choose Qmax Systems
| Capability | Qmax Advantage |
|---|---|
| First-Time-Right Methodology | SI/PI constraints are defined and verified before layout begins — not applied as post-routing corrections. This eliminates the most common cause of re-spin: a routing approach that violates SI targets and cannot be corrected without reworking large portions of the board. |
| Silicon Vendor Relationships | Over 30 years of direct engineering relationships with Broadcom, Intel, AMD, Qualcomm, NXP, Ampere, and MediaTek. We obtain silicon-validated IBIS-AMI and SPICE models and follow each vendor's platform validation checklists — the same methodology the silicon vendor's own hardware validation team uses. |
| PCB Fabricator Relationships | Direct technical collaboration with tier-1 PCB fabricators to define stackup constructions, obtain fabricator-measured Dk/Df data at frequency, confirm back-drill depth tolerance, and validate DFM feasibility before design is finalised. We have maintained these fabricator relationships for over 30 years across North America, Europe, and Asia. |
| Multi-Physics Integration | SI and PI are never analysed in isolation. PDN noise coupling into SI channels, ground bounce degrading eye margins, and thermal effects on Dk shift are all accounted for in the analysis workflow. |
| IP Ownership | All simulation files, extracted models, constraint files, and reports are customer property, delivered in industry-standard formats (Touchstone .sNp, SPICE, PDF, native tool files). |
| Compliance Readiness | SI/PI work is conducted with EMI/EMC pre-compliance in mind from day one. Return path integrity, decoupling strategies, and mode conversion suppression are aligned with CE, FCC, CISPR, and automotive CISPR 25 requirements. |
1.4 Complimentary SI/PI Review — Included with PCB Layout Services
Every PCB layout engagement at Qmax Systems includes a complimentary SI/PI review conducted before routing begins. This is a structured engineering review that covers stackup feasibility against target interface data rates, PCB material selection recommendation, critical net identification, preliminary PDN target impedance definition, via back-drill requirements, decoupling pre-placement strategy, and component placement guidelines for SI-critical devices. This early-stage review significantly reduces the probability of post-layout SI/PI failures that require stackup changes or critical net re-routing.
2. High-Speed Interface Coverage
Qmax Systems provides SI analysis across the current and emerging generations of high-speed digital interconnect standards. The table below lists the primary interfaces. Where multiple generations exist within a family, the most demanding generation is listed — our capability at that level implies full coverage of all predecessor generations in the same family.
| Interface / Standard | Data Rate & Modulation | Key SI Engineering Scope |
|---|---|---|
| PCIe Gen6 / CXL 3.x | 64 GT/s per lane, PAM4 | COM analysis per PCI-SIG CEM Spec, PAM4 three-eye mask compliance, ICN budget across x16 lane bundles, back-drill optimisation for 64GT/s, DFE tap co-optimisation, CXL 3.x memory fabric channel analysis |
| 112G PAM4 Ethernet (IEEE 802.3ck / 400G / 800G) | 112 Gbps per lane, PAM4 XSR / VSR / MR reach | OIF CEI-112G channel compliance, FEC gain budget, SNDR optimisation, 8-tap FFE + 24-tap DFE modelling, QSFP-DD / OSFP connector S-parameter extraction, host board via transition 3D EM analysis |
| 224G PAM4 Ethernet (IEEE 802.3dj — emerging) | 224 Gbps per lane, PAM4 | Ultra-low IL budget channel modelling, package co-design at board interface, advanced CDR jitter tolerance analysis, co-design with silicon vendor pre-production models |
| DDR5 / LPDDR5X (JEDEC JESD79-5 / JESD209-5) | Up to 8533 MT/s, NRZ parallel | Per-pin DQ eye simulation, DFE-assisted receiver margin, VDDQ PDN AC impedance, RDIMM/LRDIMM buffer insertion, SSO noise analysis for 64-bit bus, thin HDI via transition for LPDDR5X |
| MIPI C-PHY v2.1 / D-PHY v2.5 (CSI-2, DSI) | Up to 4.5 Gsps/Gbps per lane/trio | 100Ω differential (D-PHY) / trio impedance (C-PHY), intra-pair skew, ESD TVS capacitance loading on eye margin, fine-pitch BGA via model extraction, automotive ADAS platform compliance |
| USB4 Gen 3x2 / Thunderbolt 4 | 40 Gbps, PAM4 | Dual-role port channel SI, cable assembly channel extension, ESD / EMC filter loading on eye, compliance with USB IF and Thunderbolt specifications |
| Backplane Ethernet (100GBASE-KR4, 400GBASE-KR8) | 25G / 56G NRZ & PAM4 per lane | IEEE 802.3 channel compliance mask, full backplane IL and NEXT/FEXT extraction, connector and press-fit via modelling |
| NVLink / NVSwitch (NVIDIA GPU interconnect) | High-speed proprietary SerDes | Inter-GPU differential channel SI over long board traces (up to 600mm), connector and cable channel extension modelling, co-design with NVIDIA platform guidelines |
2.1 NRZ vs. PAM4 — Engineering Implications
The industry transition from NRZ (binary, 2-level) to PAM4 (4-level Pulse Amplitude Modulation) above 56Gbps per lane has fundamentally changed the SI engineering challenge. PAM4 encodes 2 bits per symbol, achieving twice the data rate at the same baud rate — but each of the three superimposed eyes is only one-third of the full NRZ swing, imposing a 9.5dB SNR penalty. This means PAM4 channels must operate with significantly tighter insertion loss (SDD21), lower integrated crosstalk noise (ICN from NEXT and FEXT), and more sophisticated receiver equalization — CTLE, DFE with 4 to 24 taps, and in some implementations MLSE (Maximum Likelihood Sequence Estimation) — to meet the BER targets required before FEC (Reed-Solomon Forward Error Correction) gain is applied.
COM (Channel Operating Margin) analysis per IEEE 802.3 and PCI-SIG is the standard assessment methodology for PAM4 channel compliance. COM incorporates channel IL, ICN, equalization settings, transmitter noise, and receiver sensitivity into a single figure of merit — a COM value below 3dB constitutes a channel failure. Qmax runs COM analysis for all PCIe Gen5/6 and 112G/224G PAM4 designs as a standard deliverable.
3. PCB Material Selection for SI/PI Performance
PCB laminate material selection is one of the most consequential decisions in high-speed board design. The dielectric constant (Dk) and dissipation factor (Df) of the laminate directly determine signal propagation velocity, controlled impedance, and per-unit-length channel insertion loss at the operating frequency. Qmax engineers work directly with PCB fabricators to obtain measured material data at frequency — not just 1MHz datasheet values — and incorporate this into channel simulation before the stackup is finalised.
3.1 Laminate Properties and Their SI Significance
| Material Property | SI Significance | Values at 10GHz by Material Class |
|---|---|---|
| Dissipation Factor (Df / tanδ) | Primary source of dielectric insertion loss. Higher Df = higher loss per unit length. The most critical parameter for channels above 16GT/s. |
|
| Dielectric Constant (Dk / εr) | Determines signal propagation velocity and controlled impedance. Dk is frequency-dependent (dispersion) — must be characterised at operating frequency, not DC. |
|
| Copper Foil Roughness (Ra) | Skin effect at high frequency confines current to the conductor surface; rougher copper extends the effective path length, increasing conductor loss. Standard (STD ED) foil imposes 30–50% excess conductor loss vs. HVLP at 10GHz. |
|
| Glass Weave Style & Resin Content | Periodic glass fiber structure creates spatially varying local Dk beneath routed traces (fiber weave effect), causing differential pair skew and mode conversion (SCD21). Resin-rich constructions (RC > 70%) and 1080/1067 weave styles reduce the Dk variation amplitude. |
|
| Water Absorption (% by weight) | Absorbed moisture shifts Dk/Df, degrading SI performance in humidity. Low-absorption laminates required for field-deployed equipment. |
|
3.2 Material Selection by Interface Speed
| Interface Speed Range | Laminate Recommendation | Key Selection Basis |
|---|---|---|
| Up to 16GT/s / 10Gbps NRZ | Isola 370HR, Panasonic R-1566, Ventec VT-47 | Moderate Df acceptable. Standard FR-4 class. Cost-optimised. |
| 16–32GT/s / 10G–25G NRZ | Isola I-Tera MT40, Panasonic Megtron 6 | Df ≤0.005 at 10GHz required. VLP copper foil specified. Megtron 6 is the production standard at this tier. |
| 32–64GT/s / 56G NRZ – 64G PAM4 (PCIe Gen5/6) | Panasonic Megtron 6 / Megtron 7, Isola Tachyon 100G, Ventec VT-901 | Df ≤0.003 at 10GHz mandatory. HVLP copper required. Tight Dk tolerance (±0.05) specified. Resin-rich prepregs for all critical signal layers. |
| 112G PAM4 and above | Panasonic Megtron 7, Isola Tachyon 100G, Taconic TLY, experimental laminates | Ultra-low Df (≤0.0025 at 10GHz). HVLP copper with Huray/Hammerstad roughness model in simulation. Co-designed with fabricator on material lot basis. |
| RF / Microwave sections in mixed stackups | Rogers 4350B, Rogers 4003C, Taconic RF-35 | Stable Dk vs. frequency. Low Df for mmWave content. Hybrid stackup construction with fabricator engineering team. |
For every design above 25Gbps per lane, Qmax specifies fiber weave direction, glass style per layer, copper foil type, and resin content in the fabrication notes. These are transmitted to the PCB fabricator as part of the stackup specification document, and confirmed as processable by the fabricator before design release.
4. SI/PI Simulation Methodology & Tools
Qmax applies a layered simulation methodology, selecting the appropriate tool and model depth based on interface speed, channel complexity, and project phase. The methodology progresses from 2D/RLGC extraction for pre-layout feasibility through full 3D EM extraction and statistical IBIS-AMI eye simulation for final verification.
| Analysis Type | Tools | Application |
|---|---|---|
| 2D Field Solver / RLGC Extraction | Ansys 2DExtractor, Cadence Sigrity SpeedXP | Pre-layout impedance calculation, trace width/spacing optimisation, differential pair geometry for Ztarget |
| 3D EM Via & Connector Modelling | Ansys HFSS, CST Studio Suite | Via stub resonance, BGA fanout via S-parameter extraction, connector SDD21/SDD11, back-drill depth optimisation, anti-pad geometry |
| Channel IBIS-AMI Simulation | Ansys SIwave Channel Designer, Cadence Sigrity SystemSI | End-to-end statistical eye diagram with TX FFE / RX CTLE / DFE models from silicon vendors. BER bathtub curve, jitter budget. |
| COM Analysis | IEEE 802.3 COM MATLAB reference tool, vendor-specific COM platforms | PCIe Gen5/6 and 112G/224G PAM4 channel pass/fail per IEEE COM. ICN, ISI, and equalization co-optimisation. |
| PDN DC IR Drop | Ansys PowerDC, Cadence Sigrity PowerDC | Full-board DC current distribution, plane hotspot mapping, via current density, multi-rail co-simulation |
| PDN AC Impedance | Ansys SIwave, Cadence Sigrity PowerSI | PDN impedance vs. frequency, anti-resonance identification, decoupling capacitor sweep and placement optimisation |
| TDR / Time Domain | Ansys SIwave, Keysight ADS | Impedance profiling of critical nets, discontinuity identification, correlation with physical TDR measurements at bring-up |
| SPICE / Transient | HSpice, Spectre, LTspice | Termination network simulation, PDN transient response under load step, SSO noise, power sequencing analysis |
5. Representative SI Analysis Results — Actual Qmax Project Data
The following simulation outputs are from production SI analysis engagements conducted by Qmax Systems. They represent the type of analysis artefacts delivered to customers as standard project deliverables.
5.1 PAM4 Eye Diagram — Worst-Case Eye Margin
Ansys QuickEye IBIS-AMI statistical eye simulation. End-to-end PAM4 channel with TX FFE equalization and RX CTLE/DFE. Result: inner eye height 104.6mV, eye width 34.7ps. The three superimposed eyes characteristic of PAM4 signalling are visible. The probability density heatmap (red = highest density) confirms clean eye opening. Eye height and width are evaluated against the specification compliance mask to establish pass/fail margin for the channel.
5.2 Board TDR Analysis — Via Impedance Discontinuity Identification
Ansys SIwave / HFSS transient impedance simulation for a Broadcom SoC differential pair channel. The plot identifies three impedance discontinuities in the BGA fanout and via transition zone: a BGA pad impedance dip requiring an anti-pad void under the SoC pad to recover the 95Ω differential target; a via transition impedance peak corrected by adjusting the via and anti-pad geometry; and a P/N differential pair separation causing impedance rise to 100Ω, corrected by maintaining matched P/N via spacing. This iterative TDR-guided optimisation is performed for all critical via types before design rules are locked.
5.3 Differential Insertion Loss & Return Loss (SDD21 / SDD11)
Ansys HFSS mixed-mode S-parameter extraction for multiple differential pairs from DC to 25GHz. SDD21 (differential insertion loss) and SDD11 (differential return loss) are plotted for all lanes with a reference marker at 8GHz Nyquist. Worst-case SDD21 at 8GHz: −15.86dB; worst-case SDD11: −9.85dB. These values are assessed against the applicable IEEE or JEDEC channel compliance mask to determine pass/fail margin and — where insufficient margin exists — to drive back-drill depth, trace length, or material changes.
5.4 NEXT Analysis — Near-End Crosstalk Across All Lane Combinations
Ansys SIwave / HFSS NEXT extraction for all aggressor-victim differential pair combinations in a multi-lane interface. Worst-case NEXT at 8GHz: −38.12dB; best-case: −80.68dB. These NEXT values are inputs to the COM ICN calculation — the statistical aggregate of all crosstalk contributions at the receiver. For PAM4 channels, where each eye opening is approximately 9.5dB smaller than an equivalent NRZ eye, maintaining NEXT and FEXT below the ICN budget is a primary routing discipline constraint.
6. Applications & Real Project Experience
Qmax Systems has delivered production-qualified SI/PI analysis across the following interfaces and power delivery categories. Each represents multiple customer programs, not isolated engagements.
6.1 Ethernet — 10Gbps through 100Gbps
10GBASE-KR / 25GBASE-KR through 100GBASE-KR4 and 100GBASE-KP4 PAM4 backplane and host-board channels. Full SDD21/SDD11 analysis, IBIS-AMI receiver equalization simulation per IEEE 802.3, COM analysis for PAM4 lanes, QSFP28 host board via transition 3D EM extraction, PDN analysis for Ethernet switch ASICs with 50A+ switching current demands. Retimer placement and channel loss budget optimisation for reach extension.
6.2 PCIe Gen6 / CXL 3.x
64GT/s PAM4 end-to-end channel COM analysis from CPU/GPU die pad through package, PCB trace, connector, and endpoint. Via stub resonance analysis and back-drill depth specification for server-class board thicknesses. IBIS-AMI simulation with silicon-validated FFE/CTLE/DFE models from Intel, AMD, Broadcom, and Qualcomm. ICN budget management across x16 lane bundles in high-lane-count switch and NIC designs. PDN analysis for PCIe Gen6 switch ICs on AI accelerator fabrics. All prior PCIe generations (Gen3/4/5) are covered as a subset of this capability.
6.3 MIPI CSI-2 (D-PHY & C-PHY)
MIPI D-PHY v2.5 at 4.5Gbps and C-PHY v2.1 at 4.5Gsps for camera sensor and display interfaces. Differential pair and trio impedance control on thin HDI substrates. Intra-pair skew analysis, ESD protection TVS device capacitance loading on eye margin, fine-pitch BGA via model extraction for mobile and automotive ADAS camera SoC platforms. Co-analysis with Qualcomm, MediaTek, and NXP platform design guidelines.
6.4 DDR4 & DDR5 Memory Subsystems
DDR4-3200 through DDR5-8400 and LPDDR5X at 8533 MT/s. Fly-by command/address topology simulation, per-pin DQ eye analysis with DFE-assisted receiver margin, ODT sweep optimisation, VDDQ PDN AC impedance profiling with RDIMM/LRDIMM buffer models, SSO noise analysis for 64-bit data bus simultaneous switching. Point-to-point LPDDR5X routing SI on thin HDI PCBs for mobile SoC platforms.
6.5 High-Current Power Supply PI Analysis
Multi-phase VRM output PDN analysis for 100A–500A CPU, GPU, and ASIC power rails. DC IR drop with copper thickness selection per IPC-2152. AC PDN impedance from 100Hz to 500MHz, anti-resonance suppression through capacitor bank optimisation. VRM output transient response for 300A/μs load steps typical of high-core-count server processors. PDN analysis for power electronics boards with heavy copper (4oz+) and bus bars.
6.6 Multi-CPU Board PI Analysis
Dual and quad-socket server PDN co-simulation: per-socket VRM co-design, cross-socket reference plane coupling analysis, bulk capacitor placement optimisation for each socket power delivery zone. Inter-socket UPI/xGMI SI analysis across full board dimensions. Thermal-PDN co-simulation incorporating power plane temperature rise under sustained peak CPU workloads.
6.7 AI Accelerator — PCIe Gen6 Switch SI & PI
PCIe Gen6 / CXL 3.x switch fabric COM analysis for 128+ lane PAM4 topologies. Full-board PDN for GPU accelerator platforms at 700W+ per device: sub-milliohm Ztarget PDN design, 300A load step transient simulation, Broadcom and Marvell switch ASIC power domain PI. NVLink/NVSwitch inter-GPU differential channel SI over long board traces with cable assembly channel extension. Thermal-PDN co-simulation for sustained AI training workloads.
7. Silicon Vendor & PCB Fabricator Coordination
The most common cause of first-prototype SI/PI failures is a mismatch between simulation assumptions and the actual manufactured board and device behaviour. Qmax Systems eliminates this through direct, engineering-level relationships with both silicon vendors and PCB fabricators — relationships built and maintained over more than 30 years of collaborative program execution.
7.1 Silicon Vendor Collaboration
| Silicon Vendor | Collaboration Scope |
|---|---|
| Broadcom | PCIe Gen4/5/6 IBIS-AMI models, Ethernet PHY SI platform guidelines, Trident/Tomahawk switch SI validation checklists. BGA fanout via optimisation as shown in TDR Figure 2. |
| Intel | Xeon/Core PCIe Gen5 CEM SI guidelines, DDR5 memory subsystem design rules, EMIB/Foveros package interface models, VR12.5 PDN co-design specifications. |
| AMD | EPYC/Ryzen PCIe Gen5 SI validation, MI-series GPU power delivery PDN specifications, DDR5 memory interface design rules, LRDIMM channel simulation models. |
| Qualcomm | Snapdragon LPDDR5X SI routing guidelines, MIPI CSI-2 D-PHY/C-PHY models, automotive ADAS platform SI/PI design packages, 5G co-existence SI. |
| NXP Semiconductors | Layerscape/S32 PCIe/DDR SI guides, automotive Ethernet 100BASE-T1/1000BASE-T1 channel models, CAN-FD physical layer SI. |
| Ampere Computing | Altra/AmpereOne PCIe Gen4/5 SI guidelines, DDR4/DDR5 memory subsystem rules, cloud-native compute platform PDN specifications. |
| MediaTek | Dimensity LPDDR5/5X SI routing rules, UFS/PCIe interface design guides, Wi-Fi 7 co-existence SI. |
7.2 PCB Fabricator Coordination
For every SI-critical design, our fabricator engagement includes obtaining fabricator-measured Dk/Df data at operating frequency from the specific material lot to be used; requesting impedance test coupon data from prior production runs on the same construction to calibrate simulation models; confirming HVLP or VLP copper foil availability and lamination process compatibility; reviewing back-drill depth tolerance achievable on the target via drill diameter; and validating HDI blind/buried via aspect ratios for fine-pitch BGA signal escapes. Etch factor compensation — the difference between artwork trace width and post-etch conductor width — is characterised per process and incorporated into impedance simulation, as this affects target impedance by 2–5Ω and is a common source of first-build impedance miss.
8. Complimentary SI/PI Schematic Review
All PCB layout engagements at Qmax Systems include a complimentary SI/PI-focused schematic review prior to layout commencement. For standalone SI/PI analysis engagements, an equivalent review is performed as the project kick-off activity.
- Termination network validation: source series resistor values, AC-coupled termination networks, ODT configuration versus channel topology and target reach
- Decoupling topology review: ferrite bead selection, bulk and ceramic capacitor value strategy per power domain, VRM output filter network adequacy
- Clock distribution SI review: driver type (LVDS/LVPECL/CML), fan-out topology, stub elimination strategy, reference plane requirements
- SerDes configuration review: TX pre-emphasis and de-emphasis settings, RX CTLE/DFE register configuration compatibility with channel loss budget
- Power sequencing review: VRM enable sequence compliance with silicon vendor power-on timing requirements
- Component lifecycle review: decoupling capacitors, termination resistors, and clock buffers in critical SI paths checked against EOL and allocation risk
The schematic review is delivered as a written findings report with change recommendations referenced to schematic sheet and component reference designator.
9. 1-Hour Complimentary Engineering Consultation
Qmax Systems offers a no-obligation, 1-hour technical consultation with senior SI/PI engineers. This is an engineering session — not a sales presentation. We review your specific interface requirements and provide direct technical input on:
- Interface feasibility: target data rate versus proposed stackup and channel length — passive channel, retimer, or redriver?
- Material selection recommendation based on interface speed and insertion loss budget
- Back-drill requirement: does your board thickness and data rate combination require controlled-depth drilling?
- PDN complexity assessment: VRM co-design requirements and Ztarget estimate
- Simulation methodology: 2D/RLGC, full 3D EM via extraction, or IBIS-AMI statistical eye — what does your channel require?
- Fabricator guidance: which fabricators can process your target laminate and back-drill specification
- Risk identification: the interfaces and power delivery items most likely to cause first-pass failure
- Review of any existing bring-up failures, TDR anomalies, or eye diagram compliance issues
Schedule Your 1-Hour SI/PI Consultation
Available for new designs, designs-in-progress, or existing designs with SI/PI issues. No project commitment required.
10. SI/PI Analysis Deliverables
| Deliverable | Content |
|---|---|
| SI Channel Analysis Report | Per-channel SDD21/SDD11 plots, eye diagram with mask overlay, IBIS-AMI bathtub BER curve, COM result, timing margin summary, pass/fail vs. specification limit |
| PDN Impedance Report | AC PDN impedance plots DC–1GHz+ per domain, Ztarget overlay, anti-resonance annotation, decoupling capacitor BOM and placement coordinates |
| DC IR Drop Report | Full-board voltage distribution maps per rail, max/min voltage annotation, hotspot identification, copper geometry modification recommendations |
| TDR Simulation Report | Impedance vs. time for critical nets, discontinuity identification with corrective action notes, BGA fanout via optimisation results |
| Stackup Specification | Layer stack with dielectric thickness, copper weight, material, controlled impedance table with tolerance, glass style and copper foil type per layer, fabricator-confirmed |
| 3D Via Model Library | HFSS/CST-extracted Touchstone .s4p S-parameter files for all critical via types, calibrated to fabricator process data |
| Constraint Files | Native PCB tool constraint files (Allegro / Altium / Zuken) with differential pair rules, length matching windows, impedance rules, via rules — pre-populated for layout engineer use |
| Simulation Project Files | All native simulation project files delivered as customer IP (Ansys SIwave/HFSS, Cadence Sigrity, HSpice) for future design reuse |
Start Your SI/PI Engagement
Whether you are developing a PCIe Gen6 AI accelerator fabric, a DDR5 server memory subsystem, a 100Gbps data centre switch, or need an independent SI/PI review of an existing design before fabrication, Qmax Systems has the engineering depth, silicon vendor relationships, and fabricator partnerships to ensure your design is correct before it is built.
Frequently asked questions.
Q1: Do you offer SI/PI analysis as a standalone service, without PCB layout?
Yes. Standalone SI/PI analysis is a primary service offering. We perform analysis on designs laid out by third parties, designs received from ODM or EMS partners, and as a pre-fabrication sign-off review. We accept Cadence Allegro, Altium Designer, Zuken CR-8000, and Mentor PADS layout files. No PCB layout commitment is required.
Q2: At what data rate does a design require SI analysis?
SI analysis is strongly recommended for single-ended interfaces above 200Mbps or differential interfaces above 1Gbps. For PCIe Gen3 and above, DDR4/DDR5, 10G+ Ethernet, and MIPI CSI-2, SI analysis is necessary for first-pass success. At PCIe Gen5/6 and 112G PAM4 Ethernet, it is not optional — channel compliance is defined by COM analysis which cannot be assessed without simulation.
Q3: What is the difference between NRZ and PAM4 in terms of SI requirements?
PAM4 encodes 2 bits per symbol across four voltage levels, with each eye opening approximately 9.5dB smaller than an NRZ eye at equivalent swing. This requires tighter insertion loss (SDD21) budgets, lower integrated crosstalk noise (ICN), more aggressive receiver equalization (CTLE + DFE with 4–24 taps), and mandatory FEC (Reed-Solomon). COM analysis per IEEE 802.3 is the standard methodology for PAM4 channel compliance. All PCIe Gen6 and 112G+ Ethernet channels are PAM4.
Q4: What PCB materials do you recommend for PCIe Gen6 and 112G PAM4 designs?
For PCIe Gen6 (64GT/s PAM4) and 112G PAM4 Ethernet, we require ultra-low-loss laminates with Df ≤0.003 at 10GHz: Panasonic Megtron 6 or Megtron 7, Isola Tachyon 100G, or Ventec VT-901. HVLP copper foil (Ra < 0.4μm) is mandatory. For 224G PAM4 emerging interfaces, Megtron 7 and experimental low-loss constructions are evaluated on a per-fabricator basis. Material selection is confirmed with the specific fabricator for available constructions and lot-measured Dk/Df data.
Q5: What is via back-drilling and when is it required?
Back-drilling removes the unused via stub below the last active signal connection, eliminating the quarter-wave stub resonance. Resonant frequency = c / (4 × stub_length × √Dk). For a 30-mil stub on Megtron 6 (Dk 3.6), resonance is approximately 13GHz — within the PCIe Gen5 Nyquist band. Back-drilling is required on boards thicker than approximately 1.6mm for PCIe Gen4, and essentially mandatory for Gen5/6 on standard server board thicknesses of 2.4–3.2mm. We calculate required back-drill depth for every design above 16GT/s and confirm tolerance achievability with the fabricator.
Q6: What is COM analysis and why is it required for PCIe Gen6?
COM (Channel Operating Margin) is the IEEE-defined figure of merit for high-speed channel compliance. It combines channel insertion loss, integrated crosstalk noise (ICN from all aggressor lanes), transmitter and receiver equalization, jitter, and noise into a single dB margin value. COM ≥ 3dB = pass. COM is mandatory for PCIe Gen5/6 per PCI-SIG and for 25G/100G/400G/800G Ethernet per IEEE 802.3. Qmax delivers COM analysis as a standard output for all applicable interfaces.
Q7: How do you obtain IBIS-AMI models for SI simulation?
We obtain silicon-validated IBIS-AMI models directly from silicon vendor application engineering teams — Broadcom, Intel, AMD, Qualcomm, NXP, Ampere, and MediaTek — through direct engineering relationships maintained for over 30 years. These models accurately capture transmitter FFE settings and receiver CTLE/DFE algorithms. Using unvalidated generic models is a common source of over-optimistic simulation results that fail to predict board-level SI failures.
Q8: How does fiber weave effect impact differential pair routing, and how is it mitigated?
The periodic glass fiber weave in PCB laminates creates spatially varying local Dk beneath differential pair traces. When P and N conductors overlie different weave regions, differential propagation velocity skew results — generating mode conversion (SCD21) and differential eye degradation. For interfaces above 10Gbps, Qmax specifies skew-angle routing (5–10° to the fiber weave direction), resin-rich prepregs (RC > 70%), and 1080/1067 glass style for critical signal layers.
Q9: What is PDN target impedance and how is it calculated?
Ztarget = ΔV / ΔI, where ΔV is the allowed supply ripple and ΔI is the maximum instantaneous current transient. For a server CPU drawing 200A with 50mV allowable droop on a 1.8V rail, Ztarget = 0.25mΩ. Achieving sub-milliohm Ztarget requires multi-phase VRM co-design, precisely calculated bulk capacitor banks, and ceramic decoupling optimised for both value and ESL — all driven by AC PDN impedance simulation, not rules of thumb.
Q10: Can you analyse power delivery for AI accelerators with 700W+ per GPU?
Yes. AI accelerator PDN is an area of specific Qmax depth. We perform full-board DC IR drop, multi-phase VRM co-design for 600–800W GPU power domains, bulk and ceramic decoupling optimisation targeting sub-milliohm Ztarget, and thermal-PDN co-simulation for sustained AI training workloads. PDN performance at these power levels is analysed as a coupled system with PCIe Gen6 reference plane SI.
Q11: How does PDN design affect SI channel performance?
PDN noise couples into SI performance through two primary paths: supply noise on TX VDD causes output common-mode injection into differential pairs, adding jitter; and ground bounce on PCB reference planes raises the effective noise floor at the receiver, degrading eye margin. A PDN that meets DC IR drop requirements can still cause PAM4 eye failures if its AC impedance is too high in the frequency band where the load switches. Qmax treats SI and PI as a coupled system throughout the analysis workflow.
Q12: Do you perform SI/PI analysis for automotive-grade electronics?
Yes. Automotive SI/PI adds AEC-Q200 component qualification for passive components in SI paths, CISPR 25 pre-compliance for in-vehicle radiated emissions, and ISO 26262 FMEA-level failure mode analysis for ASIL implications. We have experience with 100BASE-T1 / 1000BASE-T1 automotive Ethernet, CAN-FD physical layer, and MIPI CSI-2 for ADAS surround-view camera systems, co-ordinated with NXP and Qualcomm automotive platform guidelines.
Q13: How does copper foil roughness affect SI and what types do you specify?
Skin effect at high frequency confines current to the conductor surface; rougher copper forces the current to follow a longer effective path, increasing conductor loss. Standard ED copper (Ra 2–4μm) imposes 30–50% excess conductor loss versus HVLP foil (Ra < 0.4μm) at 10GHz. For all channels above 16GT/s, Qmax specifies VLP or HVLP copper foil in the stackup specification, confirmed as available with the fabricator before design release. Roughness is modelled using the Huray or Hammerstad model in the simulation tool.
Q14: Can you support board bring-up and SI/PI debug on physical prototypes?
Yes. We provide bring-up support covering eye diagram measurement methodology, TDR measurement procedure for via impedance verification, VNA S-parameter measurement setup, and PDN noise measurement technique. When simulation and measurement diverge, we investigate fabricated stackup compliance by requesting impedance test coupon results from the fabricator, verify copper foil type, and correlate simulated via impedance profiles against physical TDR traces to identify root cause.
Q15: Do you perform SI/PI analysis for rigid-flex and HDI designs?
Yes. Rigid-flex introduces SI challenges at the flex-to-rigid transition: polyimide dielectric (Dk ~3.4) is different from the rigid laminate Dk, requiring the flex segment to be modelled as a separate transmission line section; bending zone trace current capacity must be verified; and controlled impedance tolerance on polyimide substrates is wider than on rigid FR-4. HDI designs require blind/buried via 3D EM modelling for fine-pitch BGA signal escape. Both are handled within our standard SI/PI analysis workflow.
Q16: What surface finish do you recommend for high-speed PCBs?
ENIG is standard for general high-speed digital boards. For RF content and connectors above 20GHz, ENEPIG is preferred — the palladium barrier eliminates the high-permeability nickel layer that adds skin-effect loss at high frequency. Hard gold is specified for edge connectors with repeated mating cycles (PCIe slots, memory sockets). Surface finish selection is included in the Qmax stackup specification and confirmed with the fabricator, as it affects both connector contact resistance and high-frequency conductor loss on signal layers.
Q17: What mixed-mode S-parameters do you extract and why do they matter?
We extract the full mixed-mode S-parameter set for all SI-critical differential channels: SDD21 (differential insertion loss), SDD11 (differential return loss), SCD21 (differential-to-common-mode conversion), and SDDS41 (FEXT crosstalk). SCD21, the mode conversion coefficient, is particularly important — it quantifies asymmetry-driven energy conversion from differential to common mode, which is both a jitter contribution and a primary radiated EMI mechanism. Mode conversion is minimised through matched P/N via geometry, symmetric reference plane coverage, and consistent differential pair routing width and spacing.
Q18: How do you specify back-drill depth and what tolerances are achievable?
Back-drill depth is specified as the maximum allowable remaining stub length in mils from the last active signal connection to the drill-out endpoint. Required maximum stub length = 2950 / (Fres_GHz × √Dk). Standard fabricator tolerance is ±2 mils; tight tolerance is ±1 mil. These tolerances are confirmed with the fabricator during stackup review and incorporated into the via stub analysis as worst-case boundary conditions to ensure compliance even under process variation.
Q19: What is SSO noise and how is it managed in high-density ASIC designs?
Simultaneous Switching Output (SSO) noise — also called ground bounce — occurs when multiple I/O buffers switch simultaneously, injecting large instantaneous current transients into the device's VDD/GND supply. On high-density FPGAs and ASICs, SSO noise can cause tens-of-millivolt supply fluctuations that degrade differential SerDes eye quality through common-mode injection. We analyse SSO noise per I/O bank and recommend decoupling capacitor placement and I/O bank power supply partitioning strategies to maintain acceptable noise levels.
Q20: What compliance certifications does your SI/PI work support?
SI/PI analysis directly supports pre-compliance for CE (European Conformity), FCC Part 15 Class A/B, VCCI, CISPR 32 (multimedia equipment), CISPR 25 (automotive in-vehicle), and IEC 60601-1-2 (medical equipment EMC). Return path integrity, mode conversion suppression, and PDN decoupling strategies implemented during SI/PI analysis are the same design choices that determine radiated and conducted emissions compliance. Qmax designs for compliance from day one rather than treating EMC as a post-design correction.
Q21: What is plane resonance and how do you address it in PDN design?
Power-ground plane pairs form a parallel-plate resonant cavity. Cavity resonances create PDN impedance peaks at specific frequencies that peripheral decoupling capacitors cannot suppress, because the capacitors are outside the resonant region. Qmax addresses plane resonance through EBG (Electromagnetic Band Gap) structures etched into the power plane, resistive edge termination of the plane cavity, or plane segmentation to raise resonant frequencies above the PDN bandwidth of concern for the specific application.
Q22: Can you perform SI/PI analysis on 3D IC and chiplet package interfaces?
Yes. Multi-die packages — Intel EMIB, AMD 3D V-Cache, TSMC CoWoS — introduce die-to-die interconnect SI challenges at the package level, including through-silicon via (TSV) channel modelling, bump array via extraction, and package PDN analysis. We work with silicon vendor package models and perform PCB-to-package co-simulation to ensure board SI/PI constraints are compatible with the package interface requirements.
Q23: What is ICN (Integrated Crosstalk Noise) and why is it critical for PAM4?
ICN is the statistical RMS aggregate of all FEXT and NEXT contributions at the receiver, weighted by transmitter power spectral density and integrated over the channel bandwidth. It is a primary input to COM analysis. For PAM4 channels — where each eye is approximately 9.5dB smaller than an equivalent NRZ eye — even moderate ICN levels that would be acceptable in an NRZ design can close PAM4 eyes below the compliance mask. ICN is minimised through differential pair routing discipline: consistent reference planes, adequate inter-pair spacing, and matched via placement that avoids inter-lane coupling.
Q24: Do you provide SI/PI analysis reports for third-party design audits?
Yes. We regularly provide structured SI/PI audit reports on designs produced by third parties — ODM suppliers, external design houses, or internal teams without dedicated SI/PI expertise. The audit report covers per-channel SDD21/SDD11 and COM assessment, PDN impedance profile, decoupling strategy evaluation, stackup compliance against interface speed requirements, and a prioritised list of findings with specific corrective recommendations. These reports are used to inform go/no-go decisions before committing to prototype fabrication.
Q25: How long does a typical SI/PI engagement take?
A focused standalone analysis (single interface family, existing layout) typically requires 1–2 weeks. Full-board SI/PI integrated with PCB design, covering multiple high-speed interface families and complete PDN, requires 3–6 weeks depending on lane count and 3D EM extraction scope. Emergency bring-up debug support can begin within 24–48 hours. A detailed project schedule is provided at kickoff.
Q26: What simulation outputs are included in the standard SI/PI deliverable set?
Standard deliverables include: per-channel SDD21/SDD11 S-parameter plots, IBIS-AMI statistical eye diagrams with mask overlay, BER bathtub curves, COM analysis results, TDR impedance profiles for critical vias, AC PDN impedance plots per power domain with Ztarget overlay, DC IR drop voltage distribution maps, decoupling capacitor optimisation BOM, stackup specification document, 3D EM-extracted via model library (Touchstone .sNp), native PCB tool constraint files, and all simulation project files. All files are customer property.
Q27: Who owns the SI/PI simulation data and all deliverables?
All simulation files, extracted S-parameter models, analysis reports, constraint files, stackup specifications, and documentation are the sole intellectual property of the customer. Qmax does not retain, reuse, or share any customer design data across programs. Standard NDA applies to all engagements.
Q28: How do you handle etch compensation in impedance modelling?
Trace width after chemical etching differs from the artwork dimension due to the etch factor (lateral undercut). This deviation is typically 0.1–0.4 mils per side, depending on copper weight and fabricator process. On a 4-mil trace targeting 50Ω, a 0.3-mil bilateral undercut shifts impedance by 3–5Ω — a significant error if uncorrected. Qmax obtains etch factor data from the specific fabricator and applies it in the 2D field solver model when calculating artwork trace widths. This is included in the stackup specification delivered to the fabricator.
Q29: Can Qmax help with a design that has already failed first-pass bring-up?
Yes. Post-build SI/PI rescue is a standard service. We correlate simulation against physical TDR measurements, VNA S-parameter data, and oscilloscope eye diagrams from the prototype. When results diverge from simulation predictions, we investigate fabricated stackup compliance (requesting impedance test coupon results from the fabricator), copper foil type verification, and via geometry correlation. Root cause typically identifies stackup deviation, via stub length greater than specified, material Dk/Df deviation from the simulation model, or routing constraint violations.
Q30: How do we begin a SI/PI engagement with Qmax Systems?
Start with the 1-hour complimentary consultation described above — no commitment required. We review your interface list, proposed stackup, and schedule requirements, then define the analysis scope. Following scope agreement, we issue a fixed-price proposal with specific deliverables and schedule. Upon project initiation, you provide design files (schematics, layout if available, BOM, existing SI/PI data) and we begin the analysis workflow. Contact us at www.qmaxsys.com/contact.
